Real-Time ORB Accelerator for Embedded FPGA-based SoCs with ROS Integration
André Costa, José Duarte Lopes, Pedro Tomás, Nuno Roma, Nuno Neves
IEEE Transactions on Very Large Scale Integration Systems, Accepted (2026)
Paper PDF

Functional Validation of the RISC-V Unlimited Vector Extension
Ana Fernandes, Luis Crespo, Nuno Neves, Pedro Tomás, Nuno Roma, Gabriel Falcao
IEEE Embedded Systems Letters, July 2024
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NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators From Caches to DRAM
João Vieira, Nuno Roma, Gabriel Falcao, Pedro Tomás
IEEE Access, January 2024
Paper PDF

gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation
João Vieira, Nuno Roma, Gabriel Falcao, Pedro Tomás
IEEE Computer Architecture Letters, January 2024
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MIDAS: A Mapping Infrastructure for Configurable, Data-Streaming based Domain Specific Accelerators
Martim Bento, Nuno Neves, Pedro Tomás, Nuno Roma
SBAC-PAD '25: International Symposium on Computer Architecture and High Performance Computing, September 2025
(Accepted)

URAM-based asynchronous FIFO design for improved throughput and FPGA RAM usage
Martim Rosado, Pedro Tomás, Nuno Roma, André David
FPL '25: International Conference on Field-Programmable Logic and Applications, September 2025
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Advancing the RISC-V Performance Simulation Ecosystem with Data Prefetching
Luis Crespo, Nuno Neves, Pedro Tomás, Nuno Roma
RISCV-HPC '25: International Workshop on RISC-V for HPC at ISC, June 2025
Paper PDF

High-Throughput Packet Aggregator for the back-End DAQ of CERN CMS HGCAL Detector>
Martim Rosado, Pedro Tomás, Nuno Roma, André David
ISCAS '25: IEEE International Symposium on Circuits and Systems, May 2025
Paper PDF

Real-Time Orb Accelerator with ROS Integration for Embedded FPGA SoCs
André Costa, Pedro Tomás, Nuno Roma, Nuno Neves
ISCAS '25: IEEE International Symposium on Circuits and Systems, May 2025
Paper PDF

Stream-Driven Acceleration for Embedded RISC-V SoCs
João Maia, Ana Silveira, Gonçalo Midões, Nuno Neves, Pedro Tomás, Nuno Roma
ISCAS '25: IEEE International Symposium on Circuits and Systems, May 2025
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RVEBS: Event-Based Sampling on RISC-V
Tiago Rocha, Nuno Neves, Nuno Roma, Pedro Tomás, Leonel Sousa
DATE '25: Design, Automation and Test in Europe Conference, March 2025
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Dynamic Reconfigurable FPU for Next-Generation Transprecision Computing
Guilherme Dias, Luis Crespo, Pedro Tomás, Nuno Roma, Nuno Neves
LASCAS '25: Latin America Symposium on Circuits and Systems, February 2025
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Multi-Target DSL and MLIR Dialect for Streaming SIMD
Manuel Cerqueira da Silva, Luis Crespo, Nuno Neves, Nuno Paulino, João Bispo
LATTE '24: Workshop on Languages, Tools, and Techniques for Accelerator Design, April 2024
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A DSL and MLIR Dialect for Streaming and Vectorisation
Manuel Cerqueira da Silva, Luis Sousa, Nuno Paulino, João Bispo
ARC '24: Applied Reconfigurable Computing. Architectures, Tools, and Applications, March 2024
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Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study
Miguel Henriques, João Bispo, Nuno Paulino
RAPIDO '24: Workshop on Rapid Simulation and Performance Evaluation for Design, January 2024
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Trading Performance, Power, and Area on Low-Precision Posit MAC Units for CNN Training
Luis Crespo, Pedro Tomás, Nuno Roma, Nuno Neves
SBAC-PAD '23: IEEE International Symposium on Computer Architecture and High Performance Computing, October 2023
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Supporting RISC-V Performance Counters Through Performance Analysis Tools for Linux
João Mário Domingos, Tiago Rocha, Nuno Neves, Pedro Tomás, Nuno Roma, Leonel Sousa
ASAP '23: IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2023
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An FPGA-Based Platform to Evaluate Posit Arithmetic in Next-Generation Processors
Nuno Neves, Luís Crespo, Federico Rossi, Marco Cococcioni, Sergio Saponara, Martin Kuehn, Jens Krueger, Pedro Tomás, Nuno Roma
ISC-HPC '23: ISC High Performance, May 2023
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Extendable and Decoupled Multi-Level Intermediate Representation (MLIR) Compilation with JavaScript
Pedro Ramalho, Manuel Cerqueira da Silva, João Bispo, Nuno Paulino
Inforum, 2024
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UNIFY: Compilation and Hardware Adaptation for Unified Computing
Nuno Paulino
REC '24: XIX Jornadas sobre Sistemas Reconfiguráveis, June 2024
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Unlocking Sparse Processing with Stream-based Accelerated Systems-on-Chip
Ana Beatriz Fernandes
PhD Thesis, Electrical and Computer Engineering, Universidade de Coimbra, Expected 2028
(Ongoing)

Compiler-Driven Hardware Adaptation Towards General-Purpose Computing Acceleration
Luis Crespo
PhD Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, Expected 2027
(Ongoing)

Accelerating Memory-Bound Applications with Near-Data Processing: From Architectural Design to Full-System Simulation
João Vieira
PhD Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, April 2025
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Configurable Heterogeneous Data-Streaming Multi-Processor with Vectorial Processing Capability
Martim Bento
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, Expected 2025
(Ongoing)

Optimizing the Processors' Energy Efficiency using Deep Learning Models based on Voltage-Frequency Scaling
Tiago Lourinho
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, Expected 2025
(Ongoing)

Mapping Computations to a Stream-Oriented Domain Specific Language
André Costa Lima
MSc Thesis, Electrical and Computer Engineering, Faculdade de Engenharia da Universidade do Porto, Expected 2025
(Ongoing)

Reconfigurable Architectures for Neural-Network Accelerators with Data-Streaming Support
Ana Silveira
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, Expected 2025
(Ongoing)

Data-Streaming Support on Gemmini Tensor Architecture
João Maia
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, June 2025
Thesis PDF

Efficient Speech Recognition on the Edge with Binary Neural Networks
Frederico Roque
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, December 2024
Thesis PDF

FPGA-Accelerated ORB System for Real-time 3D Mapping Applications
André Costa
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, December 2024
Thesis PDF

Dinamically Reconfigurable Floating-Point Arithmetic Unit for Next-Generation Processors and Accelerators
Guilherme Dias
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, December 2024
Thesis PDF

UVE Streaming Engine: Hardware Implementation and Evaluation
Gonçalo Midões
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, November 2024
Thesis PDF

Runtime-Adaptable Cache Architecture for Modern Processors
Alexandre Correia
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, November 2024
Thesis PDF

Support for Streaming SIMD Paradigms Via MLIR
Manuel Cerqueira da Silva
MSc Thesis, Electrical and Computer Engineering, Faculdade de Engenharia da Universidade do Porto, September 2024
Thesis PDF

A Functional Validation Framework for the Unlimited Vector Extension
Ana Beatriz Fernandes
MSc Thesis, Electrical and Computer Engineering, Universidade de Coimbra, February 2024
Thesis PDF

Performance Monitoring and Event-based Sampling for RISC-V
Tiago Rocha
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, December 2023
Thesis PDF

Data-Streaming Engine for the Unlimited Vector Extension
Xavier Fernandes
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, December 2023
Thesis PDF

RISC-V Streaming Extension Support on the Spike Simulator
João Baptista
MSc Thesis, Electrical and Computer Engineering, Instituto Superior Técnico, Universidade de Lisboa, December 2023
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